absolute maximum ratingssupply voltage, |v cc 2 v ee | ecl output currentstorage temperature range max. junction temperature ttl output voltage input voltage max. open collector current 8v 10ma 2 65 c to 1 150 c 1 175 c 1 12v 25v p-p 15ma ds3647-12 the sp8690 and SP8691 are low power ecl variable modulus dividers, with both ecl10k and ttl/cmos compatibleoutputs. they divide by the lower division ratio when either of the ecl control inputs, pe1 or pe2, is in the high state and by the higher ratio when both are low (or open circuit). featuresn ecl and ttl/cmos compatible outputs n ac-coupled input n control inputs ecl compatible quick reference datan supply voltage: 2 52v 6 025v (ecl), 5v 6 025v (ttl) n power consumption: 70mw (typ.) n temperature range: 2 55 c to 1 125 c (a grade) 2 30 c to 1 70 c (b grade) fig. 1 pin connections - top view dg16 clock inputnc nc nc v ee ttl/cmos outputnc ecl output clock input pe1pe2 nc v cc ncnc ecl output 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 ? control inputs sp8690SP8691 sp8690 200mhz 4 4 4 4 4 10/11 SP8691 200mhz 4 4 4 4 4 8/9 ordering informationsp8690 a dg sp8690 b dg SP8691 a dg 5962-87678 (smd) (sp8690) fig. 2 functional diagram (sp8690) v cc d1 q1 d2 q2 d3 q3 d4 q4 pe1pe2 clock inputclock input ttl/cmos output ecl output q4 v ee 23 116 5 12 11 89 ecl output advance information
2 sp8690/SP8691 fig. 3 functional diagram (SP8691) characteristic maximum frequency (sinewave input)minimum frequency (sinewave input) power supply current ecl output high voltage ecl output low voltage pe input high voltage pe input low voltageclock to ecl output delay set-up time release time symbol f max f min i ee v oh v ol v inh v inl t p t s t r 200 2 085 2 18 2 093 38 min. max. 4021 2 07 2 15 2 162 9 units input = 400-800mv p-pinput = 400-800mv p-p v ee = 2 50v v ee = 2 52v (25 c) v ee = 2 52v (25 c) v ee = 2 52v (25 c) v ee = 2 52v (25 c) conditions notes mhzmhz ma vv v v nsns ns 55 5 6 3, 64, 6 electrical characteristics unless otherwise stated, the electrical characteristics are guaranteed over specified supply, frequency and temperature range ecl operation supply voltage, v cc = 0v, v ee = 2 52v 6 025v temperature, t amb = 2 55 c to 1 125 c (a grade), 2 30 c to 1 70 c (b grade) notes1. the temperature coefficients of v oh = 1 163mv/ c, v ol = 1 094mv/ c and of v in = 1 122mv/ c. 2. the test configuration for dynamic testing is shown in fig.8 3. the set-up time t s is defined as the minimum time that can elapse between l ? h transition of control input and the next l ? h clock pulse transition to ensure that division by the lower modulus is obtained. 4. the release time t r is defined as the minimum time that can elapse between h ? l transition of control input and the next l ? h clock pulse transition to ensure that division by the higher modulus is obtained. 5. sp8690/1b tested at 25 c only. 6. guaranteed but not tested. 7. the open collector output is not recommended for use at output frequencies above 15mhz. c load 5pf. characteristic maximum frequency (sinewave input)minimum frequency (sinewave input) power supply current ttl output low voltage ttl output high voltage clock to ttl output high delay, 1 ve going clock to ttl output low delay, 2 ve going set-up timerelease time symbol f max f min i ee v ol v oh t plh t phl t s t r 200 375 38 min. max. 4021 05 3218 units input = 400-800mv p-pinput = 400-800mv p-p v cc = 50v v cc = 5v, r l = 560 w r l = 560 w r l = 560 w r l = 560 w conditions notes mhzmhz ma vv nsns ns ns 55 5 5, 75, 7 66 3, 64, 6 ttl operation supply voltage, v cc = 5v 6 025v, v ee = 0v temperature, t amb = 2 55 c to 1 125 c (a grade), 2 30 c to 1 70 c (b grade) value value v cc d1 q1 d2 q2 d3 q3 d4 q4 pe1pe2 clock inputclock input ttl/cmos output ecl output q4 v ee 23 116 5 12 11 89 ecl output q2
3 sp8690/SP8691 l h l h pe1 ll hh truth table for control inputs 98 8 8 pe2 division ratio l h l h pe1 ll hh truth table for control inputs 1110 10 10 pe2 division ratio fig. 5 timing diagram, SP8691 fig. 4 timing diagram, sp8690 12001000 800600 400 200 0 0 50 100 150 200 250 input frequency (mhz) input amplitude (mv p-p) * tested as specified in table of electrical characteristics guaranteed * operating window 1 125 c 2 55 c fig. 7 typical input impedance. test conditions: supply voltage = 5.0v, ambient temperature = 25 c. frequencies in mhz, impedances normalised to 50 w . fig. 6 typical input characteristics, sp8690/1 6 t r t s 5 5 clock input pe inputs ecl and ttl outputs 5 5 t r t s 4 4 clock input pe inputs ecl and ttl outputs 4 j 2 j 1 j 0.5 j 0.2 0 2 j 0.2 2 j 0.5 2 j 1 2 j 2 1 0.5 0.2 j 5 2 j 5 2 5 50 100 150 200
4 sp8690/SP8691 dut 450 0.1 m outputs tosampling scope v ee 5 98 2 1 16 10n 10n 33 33 20 input from generator input monitor 450 0.1 m 24k 0.1 m v cc 560 11 31 2 q4q4 fig. 8 test circuit for dynamic measurements fig. 9 typical application showing interfacing. operating notes 1. the clock inputs can be single or differentially driven. theclock input is biased internally and is coupled to the signal source with a suitable capacitor. the input signal path is completed by an input reference decoupling capacitor which is connected to ground. 2. in the absence of a signal the device will self-oscillate. if this is undesirable, it may be prevented by connecting a 68k w resistor from the input to v ee i.e., from pin 1 or pin 16 to pin 12. this reduces the input sensitiviy by approximately100mv. 3. the circuit will operate down to dc but slew rate must be better than 100v/ m s. 4. the q 4 and q 4 outputs are compatible with eclii but can be interfaced to ecl10k as shown in fig. 9. 5. the pe inputs are ecliii/10k compatible and includeinternal 10k w pulldown resistors. unused inputs can therefore be left open circuit.6. the input impedance of the sp8690/1 varies as a function of frequency. see fig. 7. 7. the ttl/cmos output is a free collector and the high state output voltage will depend on the supply that the collector load is taken to. this should not exceed 12v. 8. the rise/fall time of the open collector output waveform is directly proportional to load capacitance and load resistor value. therefore, load capacitance should be minimised and the load resistor kept to a minimum consistent with system power requirements. in the test configuration of fig. 8 the output rise time is approximately 10ns and the fall time divide by 10/11 (sp8690) 8/9 (SP8691) 9 8 3k 3k 10k 10k 23 8 116 5 bias ecl10k output 3k 68k 10n ttl control input (see truth tables, figs. 4 and 5) 10n 3k 91 o/c clock input 11 ttl output 36k 15k 560 v cc v ee
5 sp8690/SP8691 notes
6 sp8690/SP8691 headquarters operationsgec plessey semiconductors cheney manor, swindon, wiltshire sn2 2qw, united kingdom. tel: (0793) 518000 fax: (0793) 518411 gec plessey semiconductors p.o. box 660017 1500 green hills road, scotts valley, ca95067-0017 united states of america. tel (408) 438 2900 fax: (408) 438 5576 customer service centresl france & benelux les ulis cedex tel: (1) 64 46 23 45 fax : (1) 64 46 06 07 l germany munich tel: (089) 3609 06-0 fax : (089) 3609 06-55 l italy milan tel: (02) 66040867 fax: (02) 66040993 l japan tokyo tel: (3) 5276-5501 fax: (3) 5276-5510 l north america scotts valley, usa tel: (408) 438 2900 fax: (408) 438 7023. l south east asia singapore tel: (65) 3827708 fax: (65) 3828872 l sweden stockholm tel: 46 8 702 97 70 fax: 46 8 640 47 36 l uk, eire, denmark, finland & norwayswindon tel: (0793) 518510 fax : (0793) 518582 these are supported by agents and distributors in major countries world-wide. ? gec plessey semiconductors 1994 publication no. ds3647 issue no. 1.2 march 1994 this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regard ing the capability, performance or suitability of any product or service. the company reserves the right to alter without prior knowledge the specification, design or price of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to the company's conditions of sale, w hich are available on request. package details dimensions are shown thus: mm (in). 051 (002) min 16 leads at 254 (010) nom. spacing 036/058 (0014/023) 2032 (0800) max 559/787 (0220/0310) 16-lead ceramic dil e dg16 1 16 318/406 (0125/0160) pin 1 ref notch 020/036 (0008/0014) 762 (03) nom ctrs 508/(020) max 114/165 (0045/0065) seating plane notes1. controlling dimensions are inches. 2. this package outline diagram is for guidance only. please contact your gps customer service centre for further information.
|
